Hardware accelerators (HWA) are designed to perform particular functions faster than is possible with software and general-purpose processor. For example, HWAs have been used to perform mathematical operations and/or graphics operations for computing devices. For mobile computing devices, efficient operations performed by HWAs can improve battery-life and performance. There is some overhead associated with use of HWAs with other system components. Further, error recovery for HWAs can be a challenging task. In particular, as automation of tasks for a HWA architecture increases, the difficulty of error recovery likewise increases. HWA architectural complications exist, for example, due to distributed synchronization and timing differences of HWA components.